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| Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 FEATURES Low Offset Voltage: 1 V Input Offset Drift: 0.005 V/ C Rail-to-Rail Input and Output Swing 5 V/2.7 V Single-Supply Operation High Gain, CMRR, PSRR: 130 dB Ultralow Input Bias Current: 20 pA Low Supply Current: 750 A/Op Amp Overload Recovery Time: 50 s No External Capacitors Required APPLICATIONS Temperature Sensors Pressure Sensors Precision Current Sensing Strain Gage Amplifiers Medical Instrumentation Thermocouple Amplifiers PIN CONFIGURATIONS 8-Lead MSOP (RM Suffix) NC IN A IN A V 1 8 NC V+ OUT A NC 8-Lead SOIC (R Suffix) NC 1 IN A 2 +IN A 3 V 4 8 NC AD8571 4 5 NC = NO CONNECT AD8571 7 V+ 6 OUT A 5 NC NC = NO CONNECT 8-Lead TSSOP (RU Suffix) OUT A IN A +IN A V 1 8 8-Lead SOIC (R Suffix) OUT A 1 IN A 2 +IN A 3 V 4 8 V+ AD8572 4 5 V+ OUT B IN B +IN B AD8572 7 OUT B 6 IN B 5 +IN B GENERAL DESCRIPTION This new family of amplifiers has ultralow offset, drift, and bias current. The AD8571, AD8572, and AD8574 are single, dual, and quad amplifiers, respectively, featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V single supply. The AD857x family provides the benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices' topology, these zero-drift amplifiers combine low cost with high accuracy. (No external capacitors are required.) In addition, using a patented spread-spectrum auto-zero technique, the AD857x family virtually eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. With an offset voltage of only 1 mV and drift of 0.005 mV/C, the AD8571 is perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD857x family. The AD857x family is specified for the extended industrial/ automotive (-40C to +125C) temperature range. The AD8571 single is available in 8-lead MSOP and narrow 8-lead SOIC packages. The AD8572 dual amplifier is available in 8-lead narrow SOIC and 8-lead TSSOP surface mount packages. The AD8574 quad is available in narrow 14-lead SOIC and 14-lead TSSOP packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. OUT A IN A IN A V NB IN B OUT B 14-Lead TSSOP (RU Suffix) 1 14 OUT D IN D IN D V IN C IN C OUT C 14-Lead SOIC (R Suffix) OUT A 1 IN A 2 +IN A 3 V+ 4 +IN B 5 IN B 6 OUT B 7 14 OUT D 13 IN D AD8574 7 8 12 +IN D AD8574 11 V 10 +IN C 9 8 IN C OUT C One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD8571/AD8572/AD8574-SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain* Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High VOS IB IOS CMRR AVO DVOS/DT VOH (VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25 C, unless otherwise noted.) Conditions Min Typ 1 10 1.0 20 150 0 120 115 125 120 Max 5 10 50 1.5 70 200 5 Unit mV mV pA nA pA pA V dB dB dB dB mV/C V V V V mV mV mV mV mA mA mA mA dB dB mA mA V/ms ms MHz mV p-p mV p-p nV//Hz fA//Hz Symbol -40C TA +125C -40C TA +125C -40C TA +125C VCM = 0 V to 5 V -40C TA +125C RL = 10 kW, VO = 0.3 V to 4.7 V -40C TA +125C -40C TA +125C RL = 100 kW to GND -40C to +125C RL = 10 kW to GND -40C to +125C RL = 100 kW to V+ -40C to +125C RL = 10 kW to V+ -40C to +125C -40C to +125C 140 130 145 135 0.005 0.04 4.998 4.997 4.98 4.975 1 2 10 15 50 40 30 15 4.99 4.99 4.95 4.95 Output Voltage Low VOL Short Circuit Limit Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Specifications subject to change without notice. ISC IO -40C to +125C PSRR ISY VS = 2.7 V to 5.5 V -40C TA +125C VO = 0 V -40C TA +125C RL = 10 kW 25 10 10 30 30 120 115 130 130 850 975 1,000 1,075 0.4 0.05 1.5 1.3 0.41 51 2 SR GBP en p-p en p-p en in 0.3 0 Hz to 10 Hz 0 Hz to 1 Hz f = 1 kHz f = 10 Hz *Gain testing is highly dependent upon test bandwidth. -2- REV. A AD8571/AD8572/AD8574 ELECTRICAL CHARACTERISTICS Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain* Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High VOS IB IOS CMRR AVO DVOS/DT VOH (VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25 C, unless otherwise noted.) Conditions Min Typ 1 10 1.0 10 150 0 115 110 110 105 Max 5 10 50 1.5 50 200 2.7 Unit mV mV pA nA pA pA V dB dB dB dB mV/C V V V V mV mV mV mV mA mA mA mA dB dB mA mA V/ms ms MHz mV p-p nV//Hz fA//Hz Symbol -40C TA +125C -40C TA +125C -40C TA +125C VCM = 0 V to 2.7 V -40C TA +125C RL = 10 kW, VO = 0.3 V to 2.4 V -40C TA +125C -40C TA +125C RL = 100 kW to GND -40C to +125C RL = 10 kW to GND -40C to +125C RL = 100 kW to V+ -40C to +125C RL = 10 kW to V+ -40C to +125C -40C to +125C 130 130 140 130 0.005 0.04 2.697 2.696 2.68 2.675 1 2 10 15 15 10 10 5 130 130 750 950 0.5 0.05 1 2.0 94 2 2.685 2.685 2.67 2.67 Output Voltage Low VOL Short Circuit Limit Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Specifications subject to change without notice. ISC IO -40C to +125C PSRR ISY VS = 2.7 V to 5.5 V -40C TA +125C VO = 0 V -40C TA +125C RL = 10 kW 10 10 10 20 20 120 115 900 1,000 SR GBP en p-p en in 0 Hz to 10 Hz f = 1 kHz f = 10 Hz *Gain testing is highly dependent upon test bandwidth. REV. A -3- AD8571/AD8572/AD8574 ABSOLUTE MAXIMUM RATINGS 1 Package Type 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 8-Lead SOIC (R) 14-Lead TSSOP (RU) 14-Lead SOIC (R) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to VS + 0.3 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 5.0 V ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite Storage Temperature Range RM, RU, and R Packages . . . . . . . . . . . . . -65C to +150C Operating Temperature Range AD8571A/AD8572A/AD8574A . . . . . . . . . -40C to +125C Junction Temperature Range RM, RU, and R Packages . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Differential input voltage is limited to 5.0 V or the supply voltage, whichever is less. JA* JC Unit C/W C/W C/W C/W C/W 190 240 158 180 120 44 43 43 36 36 * JA is specified for worst-case conditions, i.e., JA is specified for device in socket for P-DIP packages, JA is specified for device soldered in circuit board for SOIC and TSSOP packages. ORDERING GUIDE Model AD8571AR AD8571AR-REEL AD8571AR-REEL7 AD8571ARM-R2 AD8571ARM-REEL AD8572AR AD8572AR-REEL AD8572AR-REEL7 AD8572ARU AD8572ARU-REEL AD8574AR AD8574AR-REEL AD8574AR-REEL7 AD8574ARU AD8574ARU-REEL Temperature Range -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C C C C C C C C C C C C C C C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead TSSOP 8-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC 14-Lead SOIC 14-Lead TSSOP 14-Lead TSSOP Package Option Branding R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 RU-8 RU-8 R-14 R-14 R-14 RU-14 RU-14 AJA AJA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8571/AD8572/AD8574 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. A Typical Performance Characteristics-AD8571/AD8572/AD8574 180 160 INPUT BIAS CURRENT (pA) 140 120 100 80 60 40 20 0 2.5 1.5 0.5 0.5 1.5 OFFSET VOLTAGE ( V) 2.5 30 +85 C 20 10 +25 C 0 10 40 C 20 30 0 2 3 4 1 INPUT COMMON-MODE VOLTAGE (V) 5 INPUT BIAS CURRENT (pA) VS = 2.7V VCM = 1.35V TA = 25 C 50 40 VS = 5V TA = 40 C, +25 C, +85 C 1,500 1,000 500 0 500 1,000 1,500 2,000 0 1 2 3 4 COMMON-MODE VOLTAGE (V) 5 VS = 5V TA = 125 C NUMBER OF AMPLIFIERS TPC 1. Input Offset Voltage Distribution at 2.7 V TPC 2. Input Bias Current vs. Common-Mode Voltage TPC 3. Input Bias Current vs. Common-Mode Voltage 180 160 NUMBER OF AMPLIFIERS 120 100 80 60 40 20 0 2.5 1.5 0.5 0.5 1.5 OFFSET VOLTAGE ( V) 2.5 8 6 OUTPUT VOLTAGE (mV) 140 NUMBER OF AMPLIFIERS VS = 5V VCM = 2.5V TA = 25 C 12 VS = 5V VCM = 2.5V TA = 40 C TO +125 C 10k VS = 5V TA = 25 C 1k 10 100 SOURCE 10 SINK 4 2 0 0 1 2 3 4 5 INPUT OFFSET DRIFT (nV/ C) 6 1 0.1 0.0001 0.001 1 0.01 0.1 LOAD CURRENT (mA) 10 100 TPC 4. Input Offset Voltage Distribution at 5 V TPC 5. Input Offset Voltage Drift Distribution at 5 V TPC 6. Output Voltage to Supply Rail vs. Output Current at 5 V 10k VS = 2.7V TA = 25 C INPUT BIAS CURRENT (pA) 1,000 VCM = 2.5V VS = 5V 750 SUPPLY CURRENT (mA) 1.0 5V 0.8 2.7V 0.6 OUTPUT VOLTAGE (mV) 1k 100 SOURCE 10 SINK 500 0.4 1 250 0.2 0.1 0.0001 0.001 1 0.01 0.1 LOAD CURRENT (mA) 10 100 0 75 50 25 0 25 50 75 100 125 150 TEMPERATURE ( C) 0 75 50 25 0 25 50 75 100 125 150 TEMPERATURE ( C) TPC 7. Output Voltage to Supply Rail vs. Output Current at 2.7 V TPC 8. Bias Current vs. Temperature TPC 9. Supply Current vs. Temperature REV. A -5- AD8571/AD8572/AD8574 SUPPLY CURRENT PER AMPLIFIER ( A) 800 TA = 25 C 700 600 500 400 300 200 100 0 0 60 50 40 VS = 2.7V CL = 0pF RL = 60 50 VS = 5V CL = 0pF RL = PHASE SHIFT (Degrees) 30 20 10 0 10 20 30 45 90 135 180 225 270 30 20 10 0 10 20 30 45 90 135 180 225 270 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 40 10k 100k 1M 10M FREQUENCY (Hz) 100M 40 10k 100k 1M 10M FREQUENCY (Hz) 100M TPC 10. Supply Current vs. Supply Voltage TPC 11. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V TPC 12. Open-Loop Gain and Phase Shift vs. Frequency at 5 V 60 50 CLOSED-LOOP GAIN (dB) 60 VS = 2.7V CL = 0pF RL = 2k AV = 100 50 CLOSED-LOOP GAIN (dB) AV = 100 OUTPUT IMPEDANCE ( ) 40 30 20 10 0 10 20 30 40 100 1k AV = 10 40 30 20 10 0 VS = 5V CL = 0pF RL = 2k 300 270 240 210 180 150 120 90 60 30 AV = 1 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 100 AV = 10 VS = 2.7V AV = 10 AV = +1 AV = +1 10 20 30 10k 100k FREQUENCY (Hz) 1M 10M 40 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 100 TPC 13. Closed Loop Gain vs. Frequency at 2.7 V TPC 14. Closed Loop Gain vs. Frequency at 5 V TPC 15. Output Impedance vs. Frequency at 2.7 V 300 270 VS = 5V OUTPUT IMPEDANCE ( ) 240 210 180 150 120 90 60 30 0 100 1k 10k 100k FREQUENCY (Hz) AV = 10 AV = 1 1M 10M AV = 100 VS = 2.7V CL = 300pF RL = 2k AV = 1 VS = +5V CL = 300pF RL = 2k AV = 1 2s 500mV 5s 1V TPC 16. Output Impedance vs. Frequency at 5 V TPC 17. Large Signal Transient Response at 2.7 V TPC 18. Large Signal Transient Response at 5 V -6- REV. A PHASE SHIFT (Degrees) 0 40 OPEN-LOOP GAIN (dB) 0 OPEN-LOOP GAIN (dB) AD8571/AD8572/AD8574 50 SMALL SIGNAL OVERSHOOT (%) VS = 1.35V CL = 50pF RL = AV = 1 VS = 2.5V CL = 50pF RL = AV = 1 45 40 35 30 VS = 1.35V RL = 2k TA = 25 C +OS 25 OS 20 15 10 5 0 10 100 1k CAPACITANCE (pF) 10k 5s 50mV 5s 50mV TPC 19. Small Signal Transient Response at 2.7 V TPC 20. Small Signal Transient Response at 5 V TPC 21. Small Signal Overshoot vs. Load Capacitance at 2.7 V 45 SMALL SIGNAL OVERSHOOT (%) 40 35 30 25 VS = 2.5V RL = 2k TA = 25 C 0V VIN VS = 2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10k AV = 100 VIN 0V VS = 2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10k AV = 100 +OS 20 15 10 5 0 10 100 1k CAPACITANCE (pF) OS VOUT 0V VOUT 0V 20 s BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV 1V 20 s BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV 1V 10k TPC 22. Small Signal Overshoot vs. Load Capacitance at 5 V TPC 23. Positive Overvoltage Recovery TPC 24. Negative Overvoltage Recovery VS = 2.5V RL = 2k AV = 100 VIN = 60mV p-p CMRR (dB) 140 VS = 2.7V 120 100 140 VS = 5V 120 100 CMRR (dB) 80 60 40 20 0 100 80 60 40 200 s 1V 20 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 25. No Phase Reversal TPC 26. CMRR vs. Frequency at 2.7 V TPC 27. CMRR vs. Frequency at 5 V REV. A -7- AD8571/AD8572/AD8574 140 VS = 120 100 1.35V 140 VS = 120 100 PSRR (dB) 3.0 2.5V 2.5 OUTPUT SWING (V p-p) VS = 1.35V RL = 2k AV = 1 THD+N < 1% TA = 25 C 2.0 PSRR (dB) 80 60 PSRR 40 20 0 100 +PSRR 80 +PSRR 60 PSRR 40 20 0 100 1.5 1.0 0.5 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 100 1k 10k 100k FREQUENCY (Hz) 1M TPC 28. PSRR vs. Frequency at 1.35 V TPC 29. PSRR vs. Frequency at 2.5 V TPC 30. Maximum Output Swing vs. Frequency at 2.7 V 5.5 5.0 4.5 OUTPUT SWING (V p-p) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 100 1k VS = 2.5V RL = 2k AV = 1 THD+N < 1% TA = 25 C 0V VS = 1.35V AV = 120,000 VS = 2.5V AV = 120,000 1s 50mV 1s 50mV 10k 100k FREQUENCY (Hz) 1M TPC 31. Maximum Output Swing vs. Frequency at 5 V TPC 32. 0.1 Hz to 10 Hz Noise at 2.7 V TPC 33. 0.1 Hz to 10 Hz Noise at 5 V 364 312 en (nV/ Hz) VS = 2.7V RS = 0 112 96 en (nV/ Hz) VS = 2.7V RS = 0 182 156 en (nV/ Hz) VS = 5V RS = 0 260 208 156 104 52 0 0.5 1.0 1.5 FREQUENCY (kHz) 2.0 2.5 80 64 48 32 16 0 5 10 15 FREQUENCY (kHz) 20 25 130 104 78 52 26 0 0.5 1.0 1.5 FREQUENCY (kHz) 2.0 2.5 TPC 34. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz TPC 35. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz TPC 36. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz -8- REV. A AD8571/AD8572/AD8574 150 POWER SUPPLY REJECTION (dB) 112 96 en (nV/ Hz) VS = 5V RS = 0 210 180 en (nV/ Hz) VS = 5V RS = 0 VS = 2.7V TO 5.5V 145 80 64 48 32 16 0 5 10 15 FREQUENCY (kHz) 20 25 150 120 90 60 30 0 5 FREQUENCY (Hz) 10 140 135 130 125 75 50 25 0 25 50 75 100 125 150 TEMPERATURE ( C) TPC 37. Voltage Noise Density at 5 V from 0 Hz to 25 kHz TPC 38. Voltage Noise Density at 5 V from 0 Hz to 10 Hz TPC 39. Power-Supply Rejection vs. Temperature 50 100 250 OUTPUT VOLTAGE SWING (mV) VS = 5V ISC SHORT-CIRCUIT CURRENT (mA) SHORT-CIRCUIT CURRENT (mA) 40 30 VS = 2.7V ISC 80 60 40 20 0 20 225 200 175 150 125 100 75 50 25 VS = 5V 20 10 0 10 20 30 40 50 75 50 25 0 25 50 75 100 125 150 TEMPERATURE ( C) ISC+ RL = 1k ISC+ 40 60 80 100 75 50 25 0 25 50 75 100 125 150 TEMPERATURE ( C) RL = 10k 75 50 25 RL = 100k 0 0 25 50 75 100 125 150 TEMPERATURE ( C) TPC 40. Output Short-Circuit Current vs. Temperature TPC 41. Output Short-Circuit Current vs. Temperature TPC 42. Output Voltage to Supply Rail vs. Temperature 250 225 OUTPUT VOLTAGE SWING (mV) VS = 5V 200 175 150 125 100 75 50 25 0 75 50 25 RL = 10k RL = 100k RL = 1k 0 25 50 75 100 125 150 TEMPERATURE ( C) TPC 43. Output Voltage to Supply Rail vs. Temperature REV. A -9- AD8571/AD8572/AD8574 FUNCTIONAL DESCRIPTION The AD857x family are CMOS amplifiers that achieve their high degree of precision through random frequency auto-zero stabilization. The autocorrection topology allows the AD857x to maintain its low offset voltage over a wide temperature range, and the randomized auto-zero clock eliminates any intermodulation distortion (IMD) errors at the amplifier's output. The AD857x can be run from a single supply voltage as low as 2.7 V. The extremely low offset voltage of 1 mV and no IMD products allows the amplifier to be easily configured for high gains without risk of excessive output voltage errors. This makes the AD857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/C ensures a minimum of offset voltage error over its entire temperature range of -40C to +125C. These combined features make the AD857x an excellent choice for a variety of sensitive measurement and automotive applications. Amplifier Architecture As noted in the Amplifier Architecture section, each AD857x op amp contains two internal amplifiers. One is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figures 1 and 2 these are labeled as VOSX, where X denotes the amplifier associated with the offset; A for the nulling amplifier, B for the primary amplifier. The open-loop gain for the +IN and -IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX. There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase. Auto-Zero Phase Each AD857x op amp consists of two amplifiers, a main amplifier and a secondary amplifier, used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their rds. Simply put, the output voltage will not swing as close to the rail under heavy output current conditions as it will with light output current. This is a characteristic of all rail-to-rail output amplifiers. TPCs 6 and 7 show how close the output voltage can get to the rails with a given output current. The output of the AD857x is short circuit protected to approximately 50 mA of current. The AD857x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kW. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. Open-loop gain will decrease with smaller load resistances. This is another characteristic of rail-to-rail output amplifiers. Basic Auto-Zero Amplifier Theory In this phase, all A switches are closed and all B switches are opened. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier, which maintains a potential difference between the +IN and -IN inputs. The nulling amplifier feedback loop is closed through A2 and VOSA appears at the output of the nulling amp and on CM1, an internal capacitor in the AD857x. Mathematically, we can express this in the time domain as VOA t = AAVOSA t - BAVOA t which also can be expressed as: VOA t = [] [] [] (1) [] AAVOSA t 1 + BA [] (2) This shows that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the CM1 capacitor. VIN+ AB VIN B A VOSA + AA BA A VOA B BB CM2 VOUT VNB CM1 VNA Figure 1. Autozero Phase of the AD857x Amplification Phase Autocorrection amplifiers are not a new technology. Various IC implementations have been available for over 15 years and some improvements have been made over time. The AD857x design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD857x is able to offer extremely low offset voltages and high open-loop gains. When the B switches close and the A switches open for the amplification phase, this offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier. The voltage across CM1 is designated as VNA. Let us also designate VIN as the potential difference between the two inputs to the primary amplifier, or VIN = (VIN+ - VIN-). Now the output of the nulling amplifier can be expressed as VOA t = AA VIN t - VOSA t - BAVNA t [] ( [] [ ]) [] (3) -10- REV. A AD8571/AD8572/AD8574 VIN+ AB VIN B A VOSA + VOA AA BA A B BB CM2 VNB VOUT In the amplification phase, VOA = VNB, so this can be rewritten as VOUT t = ABVIN t + ABVOSB + BB EE VOSA I AA AVIN t + 1 + BA IE I [] [] [] (9) combining terms: CM1 VOUT t = VIN t ( AB + AA BB ) + AA BBVOSA + ABVOSB 1 + BA [] [] VNA (10) Figure 2. Output Phase of the Amplifier Because A is now open and there is no place for CM1 to discharge, the voltage VNA at the present time t is equal to the voltage at the output of the nulling amp VOA at the time when A was closed. If we call the period of the autocorrection switching frequency TS, then the amplifier switches between phases every 0.5 TS. Therefore, in the amplification phase E1 VNA t = VNA It - TS I2 The AD857x architecture is optimized in such a way that AA = AB and BA = BB and BA >> 1. Also, the gain product to AABB is much greater than AB. These allow Equation 10 to be simplified to VOUT t = VIN t AA BA + AA (VOSA + VOSB ) [] [] (11) [] (4) and substituting Equation 4 and Equation 2 into Equation 3 yields: Most obvious is the gain product of both the primary and nulling amplifiers. This AABA term is what gives the AD857x its extremely high open-loop gain. To understand how VOSA and VOSB relate to the overall effective input offset voltage of the complete amplifier, we should set up the generic amplifier equation of VOA t = AAVIN t + AAVOSA [] [] [] E1 AA BAVOSA It - TS (5) I2 t- 1 + BA VOUT = k VIN + VOS , EFF ( ) (12) where k is the open-loop gain of an amplifier and VOS, EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives us VOUT t = VIN t AA BA + VOS , EFF AA BA From here, it is easy to see that For the sake of simplification, let us assume that the autocorrection frequency is much faster than any potential change in VOSA or VOSB. This is a good assumption since changes in offset voltage are a function of temperature variation or long-term wear time, both of which are much slower than the auto-zero clock frequency of the AD857x. This effectively makes VOS time invariant, and we can rearrange Equation 5 and rewrite it as (6) AA (1 + BA ) VOSA - AA BAVOSA VOA t = AAVIN t + 1 + BA [] [] (13) VOS,EFF VOSA + VOSB BA (14) [] [] or E V VOA t = AA AVIN t + OSA 1 + BA E [] [] Thus, the offset voltages of both the primary and nulling amplifiers are reduced by the gain factor BA. This takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. This autocorrection scheme is what makes the AD857x family of amplifiers among the most precise amplifiers in the world. High Gain, CMRR, PSRR (7) We can already get a feel for the auto-zeroing in action. Note that the VOS term is reduced by a 1 + BA factor. This shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Now the primary amplifier output voltage is the voltage at the output of the AD857x amplifier. It is equal to VOUT t = AB VIN t + VOSB + BBVNB [] ( [] ) (8) Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the previous section, the autocorrection architecture of the AD857x allows it to quite effectively minimize offset voltages. The technique also corrects for offset errors caused by commonmode voltage swings and power supply variations. This results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the device's entire temperature range, from -40C to +125C. REV. A -11- AD8571/AD8572/AD8574 Maximizing Performance through Proper Layout To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD857x, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 3 shows how the guard ring should be configured and Figure 4 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the noninverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. plane will help distribute heat throughout the board and will also reduce EMI noise pickup. COMPONENT LEAD VSC1 VTS1 + PC BOARD TA1 COPPER TRACE TA2 IF TA1 = TA2, THEN VTS1 + VSC1 = VTS2 + VSC2 VSC2 + SOLDER VTS2 + SURFACE MOUNT COMPONENT + Figure 5. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error RF R1 VIN R S = R1 VOUT VOUT VIN VOUT VIN AD857x A V = 1 + (RF /R1) AD8572 AD8572 NOTE: RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES VIN VOUT AD8572 Figure 6. Using Dummy Components to Cancel Thermoelectric Voltage Errors 1/f Noise Characteristics Figure 3. Guard Ring Layout and Connections to Reduce PC Board Leakage Currents V+ R1 VIN1 R2 AD8572 R2 R1 VIN2 GUARD RING Another advantage of auto-zero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz frequencies or dc precision applications. Because the AD857x amplifiers are self-correcting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced as a result of autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases. This allows the AD857x to have lower noise near dc than standard low noise amplifiers that are susceptible to 1/f noise. Random Auto-Zero Correction Eliminates Intermodulation Distortion VREF VREF V GUARD RING Figure 4. Top View of AD8572 SOIC Layout with Guard Rings Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the temperature of the junction. The most common metallic junctions on a circuit board are solder-to-board trace and solder-to-component lead. Figure 5 shows a cross-section diagram view of the thermal voltage error sources. If the temperature of the PC board at one end of the component (TA1) is different from the temperature at the other end (TA2), the Seebeck voltages will not be equal, resulting in a thermal voltage error. This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner will ensure both Seebeck voltages are equal, thus canceling the thermocouple error. Maintaining a constant ambient temperature on the circuit board will further reduce this error. The use of a ground The AD857x can be used as a conventional op amp for gains up to 1 MHz. The auto-zero correction frequency of the device continuously varies, based on a pseudo-random generator with a uniform distribution from 2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization of intermodulation distortion (IMD) products, which show up as simple broadband noise at the output of the amplifier. This noise naturally combines with the amplifier's voltage noise in a root-squared-sum fashion, resulting in an output free of IMD. Figure 7a shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded. Figure 7b shows the spectral output with the amplifier configured for a gain of 60 dB. REV. A -12- AD8571/AD8572/AD8574 0 20 40 OUTPUT SIGNAL Broadband and External Resistor Noise Considerations VS = 5V AV = 0dB 60 80 100 120 140 160 The total broadband noise output from any amplifier is primarily a function of three types of noise: Input voltage noise from the amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier. Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a root-squared-sum fashion. The full equation is given as 10 2 2 en,TOTAL = Een + 4kTrs + (in rs ) I I 1/ 2 0 1 2 3 4 5 6 7 FREQUENCY (kHz) 8 9 (15) Figure 7a. Spectral Analysis of AD857x Output in Unity Gain Configuration 0 VS = 5V AV = 60dB where: en = Input voltage noise of the amplifier in = Input current noise of the amplifier rs = Source resistance connected to the noninverting terminal k = Boltzmann's constant (1.38 10-23 J/K) T = Ambient temperature in Kelvin (K = 273.15 + C) The input voltage noise density, en, of the AD857x is 51 nV//Hz, and the input noise, in, is 2 fA//Hz. The en, TOTAL will be dominated by input voltage noise provided the source resistance is less than 172 kW. With source resistance greater than 172 kW, the overall noise of the system will be dominated by the Johnson noise of the resistor itself. Because the input current noise of the AD857x is very small, in does not become a dominant term unless rs is greater than 4 GW, which is an impractical value of source resistance. 20 OUTPUT SIGNAL 40 60 80 100 120 0 1 2 3 4 5 6 7 FREQUENCY (kHz) 8 9 10 The total noise, en, TOTAL, is expressed in volts-per-square-root Hertz, and the equivalent rms noise over a certain bandwidth can be found as Figure 7b. Spectral Analysis of AD857x Output with 60 dB Gain en = en,TOTAL BW where BW is the bandwidth of interest in Hertz. (16) Figure 8 shows the spectral output of an AD8572 configured in a high gain (60 dB) with a 1 mV input signal applied. Note the absence of any IMD products in the spectrum. The signal-to-noise (SNR) ratio of the output signal is better than 60 dB, or 0.1%. 0 VS = 5V AV = 60dB For a complete treatise on circuit noise analysis, please refer to the 1995 Linear Design Seminar book available from Analog Devices. Output Overdrive Recovery 20 OUTPUT SIGNAL 40 The AD857x amplifiers have an excellent overdrive recovery of only 200 ms from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers, as the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output. TPCs 23 and 24 show the positive and negative overdrive recovery time for the AD857x. The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to half-way between the supplies. The time from the input signal step-down to the output settling to within 100 mV of its final value is the overdrive recovery time. Most competitors' autocorrection amplifiers require a number of auto-zero clock cycles to recover from output overdrive and some can take several milliseconds for the output to settle properly. 60 80 100 120 0 1 2 3 4 5 6 7 FREQUENCY (kHz) 8 9 10 Figure 8. Spectral Analysis of AD857x in High Gain with an Input Signal REV. A -13- AD8571/AD8572/AD8574 Input Overvoltage Protection Although the AD857x is a rail-to-rail input amplifier, care should be taken to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier will correct its output to ensure the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials. This could cause excessive current to flow through internal diodes in the AD857x used to protect the input stage against overvoltage. If either input exceeds either supply rail by more than 0.3 V, large amounts of current will begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes will become forward-biased. Without current-limiting, excessive amounts of current could flow through these diodes causing permanent damage to the device. If inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA maximum. Output Phase Reversal to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 10 shows the output of an AD857x driving a 1 nF capacitor with and without a snubber network. 10 s WITH SNUBBER WITHOUT SNUBBER VS = 5V CLOAD = 4.7nF 100mV Figure 10. Overshoot and Ringing are Substantially Reduced Using a Snubber Network Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage is moved outside of the common-mode range, the outputs of these amplifiers will suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down, causing a radical shifting of internal voltages that results in the erratic output behavior. The AD857x amplifier has been carefully designed to prevent any output phase reversal, provided both inputs are maintained within the supply voltages. If one or both inputs could exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 mA. This will ensure the output will not reverse its phase. Capacitive Load Drive The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically since actual CLOAD will include stray capacitances and may differ substantially from the nominal capacitive load. Table I shows some snubber network values that can be used as starting points. Table I. Snubber Network Values for Driving Capacitive Loads CLOAD 1 nF 4.7 nF 10 nF Power-Up Behavior RX 200 W 60 W 20 W CX 1 nF 0.47 mF 10 mF The AD857x has excellent capacitive load-driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading will limit the bandwidth of the amplifier. Capacitive loads will also increase the amount of overshoot and ringing at the output. An R-C snubber network, Figure 9, can be used to compensate the amplifier against capacitive load ringing and overshoot. 5V On power-up, the AD857x will settle to a valid output within 5 ms. Figure 11a shows an oscilloscope photo of the output of the amplifier along with the power supply voltage, and Figure 11b shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 ms to settle to its final output voltage. This turn-on response time is much faster than most other autocorrection amplifiers, which can take hundreds of microseconds or longer for their output to settle. VOUT 0V AD857x VIN 200mV p-p RX 60 CX 0.47 F CL 4.7nF VOUT V+ 0V Figure 9. Snubber Network Configuration for Driving Capacitive Loads 5s BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV 1V Although the snubber will not recover the loss of amplifier bandwidth from the load capacitance, it will allow the amplifier Figure 11a. AD857x Output Behavior on Power-Up -14- REV. A AD8571/AD8572/AD8574 R2 VSY = 0V TO 5V 100k V2 V1 R1 R3 R4 R4 R3 R2 R1 VOUT VOUT 100k AD857x R2 R1 AD857x IF = , THEN VOUT = (V1 V2) Figure 11b. AD857x Test Circuit for Turn-On Time APPLICATIONS A 5 V Precision Strain Gage Circuit Figure 13. Using the AD857x as a Difference Amplifier In an ideal difference amplifier, the ratio of the resistors is set exactly equal to The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain gage. Figure 12 shows a configuration for a single supply, precision strain gage measurement system. A REF192 provides a 2.5 V precision reference voltage for A2. The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the current drive for the 350 W bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to 2 ( R1 + R2 ) RB AV = R2 R4 = R1 R3 (19) which sets the output voltage of the system to VOUT = A V (V 1 -V 2) (20) Due to finite component tolerance, the ratio between the four resistors will not be exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring to Figure 13, the exact common-mode rejection ratio can be expressed as CMRR = R1R4 + 2R2 R4 + R2 R3 2R1R4 - 2R2 R3 (17) (21) Where RB is the resistance of the load cell. Using the values given in Figure 12, the output voltage will linearly vary from 0 V with no strain to 4 V under full strain. 5V 2.5V Q1 2N2222 OR EQUIVALENT 4.0V R1 17.4k 1k A2 6 2 In the 3-op amp instrumentation amplifier configuration shown in Figure 14, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as , the worst-case CMRR of the instrumentation amplifier will be CMRRMIN = V2 REF192 4 3 1 2d AD8574-A R (22) AD8572-B 12k 20k R2 100 RG R R R R R VOUT 350 LOAD CELL 40mV FULL-SCALE A1 AD8572-A R4 100 VOUT 0V TO 4V V1 AD8574-C AD8574-B VOUT = 1 + 2R (V1 RG V2) RTRIM R3 17.4k NOTE: USE 0.1% TOLERANCE RESISTORS. Figure 12. A 5 V Precision Strain-Gage Amplifier 3 V Instrumentation Amplifier Figure 14. A Discrete Instrumentation Amplifier Configuration The high common-mode rejection, high open-loop gain, and operation down to 3 V of supply voltage makes the AD857x an excellent choice of op amp for discrete single supply instrumentation amplifiers. The common-mode rejection ratio of the AD857x is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 13 is given as E R4 E E R2 R1 VOUT = V 1 A A1 + -V 2 A R2 E R3 + R4 E E R1 Thus, using 1% tolerance resistors would result in a worst-case system CMRR of 0.02, or 34 dB. Therefore either high precision resistors or an additional trimming resistor, as shown in Figure 14, should be used to achieve high common-mode rejection. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kW resistors with 1% tolerance would require a series trimming resistor equal to 100 W. (18) REV. A -15- AD8571/AD8572/AD8574 A High Accuracy Thermocouple Amplifier Figure 15 shows a K-type thermocouple amplifier configuration with cold-junction compensation. Even from a 5 V supply, the AD8571 can provide enough accuracy to achieve a resolution of better than 0.02C from 0C to 500C. D1 is used as a temperature measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring tip immersed in a zero degree ice bath, R6 should be adjusted until the output is at 0 V. Using the values shown in Figure 15, the output voltage will track temperature at 10 mV/C. For a wider range of temperature measurement, R9 can be decreased to 62 kW. This will create a 5 mV/C change at the output, allowing measurements of up to 1000C. REF02EZ 12V 0.1 F 2 4 Figure 17 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8572 will be at or near ground. Again, a 0.1 W resistor provides a voltage drop proportional to the return current. The output voltage is given as ER VOUT = V + - A 2 RSENSE I L E R1 (24) For the component values shown in Figure 17, the output transfer function decreases from V at -2.5 V/A. RSENSE 0.1 3V 3V 0.1 F R1 100 3 8 IL V+ 6 5V S M1 Si9433 MONITOR OUTPUT D R2 2.49k G 2 1/2 AD8572 4 1 R5 40.2k R1 10.7k R9 124k 1N4148 D1 R2 2.74k R8 453 5V 10 F + 0.1 F 2 Figure 16. A High-Side Load Current Monitor V+ R2 2.49k VOUT Q1 K-TYPE THERMOCOUPLE 40.7 V/ C - + - + 8 1 R6 200 R4 5.62k R3 53.6 3 4 AD8571 0V TO 5V (0 C TO 500 C) Figure 15. A Precision K-Type Thermocouple Amplifier with Cold-Junction Compensation Precision Current Meter V+ Because of its low input bias current and superb offset voltage at single supply voltages, the AD857x is an excellent amplifier for precision current monitoring. Its rail-to-rail input allows the amplifier to be used as either a high-side or low-side current monitor. Using both amplifiers in the AD8572 provides a simple method to monitor both current supply and return paths for load or fault detection. Figure 16 shows a high-side current monitor configuration. Here, the input common-mode voltage of the amplifier will be at or near the positive supply voltage. The amplifier's rail-to-rail input provides a precise measurement, even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error. The 0.1 W resistor creates a voltage drop to the noninverting input of the AD857x. The amplifier's output is corrected until this voltage appears at the inverting input. This creates a current through R1, which in turn flows through R2. The Monitor Output is given by R1 100 1/2 AD8572 RSENSE 0.1 RETURN TO GROUND Figure 17. A Low-Side Load Current Monitor Precision Voltage Comparator The AD857x can be operated open-loop and used as a precision comparator. The AD857x has less than 50 mV of offset voltage when run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 ms on the rising edge and 8 ms on the falling edge. Care should be taken to ensure the maximum differential voltage of the device is not exceeded. For more information, refer to the Input Overvoltage Protection section. ER Monitor Output = R2 A SENSE I L E R1 (23) Using the components shown in Figure 16, the Monitor Output transfer function is 2.5 V/A. -16- REV. A AD8571/AD8572/AD8574 SPICE Macro-Model The SPICE macro-model for the AD857x amplifier is given in Listing 1. This model simulates the typical specifications for the AD857x, and can be downloaded from the Analog Devices website at www.analog.com. The schematic of the macro-model is shown in Figure 18. Transistors M1 through M4 simulate the rail-to-rail input differential pairs in the AD857x amplifier. The EOS voltage source, in series with the noninverting input, establishes not only the 1 mV offset voltage, but is also used to establish common-mode and power supply rejection ratios and input voltage noise. The differential voltages from nodes 14 to 16 and nodes 17 to 18 are reflected to E1, which is used to simulate a secondary pole-zero combination in the open-loop gain of the amplifier. The voltage at node 32 is then reflected to G1, which adds an additional gain stage and, in conjunction with CF, establishes the slew rate of the model at 0.5 V/ms. M5 and M6 are in a common-source configuration, similar to the output stage of the AD857x amplifier. EG1 and EG2 fix the quiescent current in these two transistors at 100 mA, and also help accurately simulate the VOUT vs. IOUT characteristic of the amplifier. The network around ECM1 creates the common-mode voltage error, with CCM1 setting the corner frequency for the CMRR roll-off. The power supply rejection error is created by the network around EPS1, with CPS3 establishing the corner frequency for the PSRR roll-off. The two current loops around nodes 80 and 81 are used to create a 51 nV//Hz noise figure across RN2. All three of these error sources are reflected to the input of the op amp model through EOS. Finally, GSY is used to accurately model the supply current versus supply voltage increase in the AD857x. This macro-model has been designed to accurately simulate a number of specifications exhibited by the AD857x amplifier, and is one of the most true-to-life macro-models available for any op amp. It is optimized for operation at 27C. Although the model will function at different temperatures, it may lose accuracy with respect to the actual behavior of the AD857x. CCM1 99 RCM1 D1 9 V1 8 99 RC7 17 RC3 7 1 + EOS RC1 D2 V1 50 C1 14 RC5 16 RC6 50 13 M1 11 M3 10 99 I2 RC2 CPS3 99 CPS1 70 RPS1 GSY RPS2 71 CPS2 50 50 98 C2 R2 31 + E1 + EREF 0 32 R3 98 98 98 50 G1 30 R1 EVP + D3 D4 51 + 47 EG2 EVN + M6 97 46 CF 45 + EG1 M5 0 + 98 99 72 RPS3 EPS1 73 RPS4 M4 RC8 18 RC4 12 M2 2 98 VN1 RN1 HN 80 + I1 ECM1 21 + RCM2 98 81 RN2 22 C2 Figure 18. Schematic of the AD857x SPICE Macro-Model REV. A -17- AD8571/AD8572/AD8574 SPICE Macro-Model for the AD857x * AD8572 SPICE Macro-model * Typical Values * 7/99, Ver. 1.0 * TAM / ADSC * * Copyright 1999 by Analog Devices * * Refer to "README.DOC" file for License * Statement. Use of this model indicates * your acceptance of the terms and * provisions in the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * ||||| * ||||| .SUBCKT AD8572 1 2 99 50 45 * * INPUT STAGE * M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 RC1 4 14 9E+3 RC2 6 16 9E+3 RC3 17 11 9E+3 RC4 18 12 9E+3 RC5 14 50 1E+3 RC6 16 50 1E+3 RC7 99 17 1E+3 RC8 99 18 1E+3 C1 14 16 30E-12 C2 17 18 30E-12 I1 99 8 100E-6 I2 10 50 100E-6 V1 99 9 0.3 V2 13 50 0.3 D1 8 9 DX D2 13 10 DX EOS 7 1 POLY(3) (22,98) (73,98) (81,98) + 1E-6 1 1 1 IOS 1 2 2.5E-12 * * CMRR 120dB, ZERO AT 20Hz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 50E+6 CCM1 21 22 159E-12 RCM2 22 98 50 * * PSRR=120dB, ZERO AT 1Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 10E-9 RPS4 73 98 16 * VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 51 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 (99,50) 48E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * LHP ZERO AT 7MHz, POLE AT 50MHz * E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 R2 32 33 3.7E+3 R3 33 98 22.74E+3 C3 32 33 1E-12 * * GAIN STAGE * G1 98 30 (33,98) 22.7E-6 R1 30 98 259.1E+6 CF 45 30 45.4E-12 D3 30 97 DX D4 51 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=1E-6 W=1.111E-3 M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 EG1 99 46 POLY(1) (98,30) 1.1936 1 EG2 47 50 POLY(1) (30,98) 1.2324 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=10E-6, + VTO=-1,LAMBDA=0.001,RD=8) .MODEL NOX NMOS (LEVEL=2,KP=10E-6, + VTO=1,LAMBDA=0.001,RD=5) .MODEL PIX PMOS (LEVEL=2,KP=100E-6, + VTO=-1,LAMBDA=0.01) .MODEL NIX NMOS (LEVEL=2,KP=100E-6, + VTO=1,LAMBDA=0.01) .MODEL DX D(IS=1E-14,RS=5) .ENDS AD8572 -18- REV. A AD8571/AD8572/AD8574 OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 3.00 BSC 5.00 (0.1968) 4.80 (0.1890) 8 5 4 8 5 3.00 BSC 1 4 4.90 BSC 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.60 0.40 0.25 (0.0098) 0.10 (0.0040) 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067) 0.50 (0.0196) 0.25 (0.0099) 45 0.23 0.08 SEATING PLANE COPLANARITY SEATING 0.10 PLANE 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.10 3.00 2.90 5.10 5.00 4.90 8 5 14 8 4.50 4.40 6.40 BSC 4.30 1 4 4.50 4.40 4.30 1 7 6.40 BSC PIN 1 0.15 0.05 0.65 BSC 1.20 MAX SEATING 0.20 PLANE 0.09 8 0 PIN 1 1.05 1.00 0.80 0.75 0.60 0.45 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.30 COPLANARITY 0.19 0.10 SEATING COPLANARITY PLANE 0.10 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AA COMPLIANT TO JEDEC STANDARDS MO-153AB-1 14-Lead Standard Small Outline Package [SOIC] (R-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 14 1 8 7 6.20 (0.2441) 5.80 (0.2283) 0.25 (0.0098) 0.10 (0.0039) 1.27 (0.0500) BSC 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 45 COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. A -19- AD8571/AD8572/AD8574 Revision History Location 7/03--Data Sheet changed from REV. 0 to REV. A. Page Renumbered figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Change to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 C01104-0-7/03(A) Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -20- REV. A This datasheet has been download from: www..com Datasheets for electronics components. |
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